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1 datasheet dual 20a/single 40a step-down power module ISL8240M the ISL8240M is a fully-encapsulated step-down switching power supply that can deliver up to 100w output power from a small 17mmx17mm pcb footprint. the two 20a outputs may be used independently or combined to deliver a single output of 40a. designing a high-performance board-mounted power supply has never been simpler -- only a few external components are needed to create a very dense and reliable power solution. 1.5% output voltage accuracy, differential remote voltage sensing and fast transient response create a very high-performance power system. built-in output overvoltage, overcurrent and over-temperature protection enhance system reliability. the ISL8240M is available in a thermally-enhanced qfn package. excellent efficiency and low thermal resistance permit full power operation without heat sinks or fans. in addition, the qfn package with external leads permits easy probing and visual solder inspection. related literature an1922 , ?ISL8240Meval4z dual 20a/optional 40a cascadable evaluation board setup procedure? an1923 , ?ISL8240Meval3z 40a, single output evaluation board setup procedure? features ? fully-encapsulated dual step-down switching power supply ? up to 100w output from a 17mmx17mm pcb footprint ? dual 20a or single 40a output ? up to 94% conversion efficiency ? 4.5v to 20v input voltage range ? 0.6v to 2.5v output voltage range ? 1.5% output voltage accuracy with differential remote sensing ? output overvoltage, overcu rrent and over-temperature protection ? qfn package with exposed leads permits easy probing and visual solder inspection applications ? computing, networking an d telecom infrastructure equipment ? industrial and medical equipment ? general purpose point-of-load (pol) power figure 1. complete 40a step-down power supply figu re 2. small footprint with high power density 1.0vat 40a 4.5v to 20v v out 4.7f 5x22f ISL8240M vin1 vsen2- vsen1+ en/ff1 en/ff2 vmon2 vmon1 sgnd pgnd vout1 vsen1- mode comp2 comp1 v in off 1.5k 9x100f 470pf 1k vcc r set note: all pins not shown are floating vin2 vout2 vin2 on sync 237k r sync 1 7 m m 1 7 m m 7.5mm january 7, 2015 fn8450.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL8240M 2 fn8450.2 january 7, 2015 submit document feedback table of contents pinout internal circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 efficiency performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 transient response performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 start-up and short circuit performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 programming the output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 selection of input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 selection of output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 en/ff turn on/off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 enable and voltage feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 current share . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 over-temperature protection (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 overcurrent protection (ocp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 frequency synchronization and phase lock loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 tracking function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mode programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 layout guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 current derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pcb layout pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 thermal vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 stencil pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 power loss curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 derating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ISL8240M 3 fn8450.2 january 7, 2015 submit document feedback pinout internal circuit vcc 2.2f vin1 en/ff1 pgood clkout ishare mode sync sgnd q 1 l 1 isen 1b isen 1a vout1 vsen1+ phase1 comp1 vmon1 24 17 19 3 5 6 vsen1- 7 pgnd 10k ? 20 12 filter 15 ugate1 14 pgnd 13 ldo + - diff amp1 22 + - error amp1 18 z comp1 z comp2 current sensing/ sharing gate driver lgate1 soft-start and fault logic vin2 en/ff2 q 3 q 4 l 2 isen 2b isen 2a vout2 phase2 10 16 ugate2 8 current sensing/ sharing gate driver lgate2 soft-start and fault logic vsen2+ comp2 vmon2 vsen2- 2 + - diff amp2 26 4 z comp3 z comp4 + - error amp2 internal reference internal reference 21 1 9 25 23 0.32h 0.32h 7.5k ? mode q 2
ISL8240M 4 fn8450.2 january 7, 2015 submit document feedback ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) ( note 4 ) package (rohs compliant) pkg. dwg. # ISL8240Mirz ISL8240M -40 to +125 26 ld qfn l26.17x17 ISL8240Meval3z evaluation board ISL8240Meval4z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged prod ucts are rohs compliant by eu exemption 7c-i and employ special pb-free material sets, molding compounds/die attach materials, and 100% ma tte tin plate plus anneal (e3) termination finish which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see product information page for ISL8240M . for more information on ms l, please see tech brief tb363 4. the ISL8240M is guaranteed over the full -40c to +125c inte rnal junction temperature range. note that the allowed ambient t emperature consistent with these specifications is determined by specific operating conditions, including board layout, cooling scheme and other environmental factors.
ISL8240M 5 fn8450.2 january 7, 2015 submit document feedback pin configuration ISL8240M (26 ld qfn) top view 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 comp2 mode vmon2 sync sgnd vcc vin2 pgnd phase2 n/c phase1 pgnd vin1 en/ff1 en/ff2 clkout vmon1 ishare comp1 vsen1- vsen1+ vout1 pgood vout2 vsen2+ vsen2- pin 1
ISL8240M 6 fn8450.2 january 7, 2015 submit document feedback pin descriptions pin number pin name type pin description 21, 1 vsen1-, vsen2- i output voltage negative feedback. negative input of the differential remote sense for the regulator. connect to the negative rail or ground of the load/processor, as shown in figure 24 . the negative feedback pins can be used to program the module operation conditions. see tables 3 and 5 for details. 20, 2 comp1, comp2 i/o error amplifier outputs. typically floating for dual-output use. for para llel use, a 470pf~1nf ca pacitor is recommended on the comp pins of each slave phase to eliminate the coupling noise. all comp pins of slave phases need to tie to master phase comp1 pin (first phase). in ternal compensation networks are implemented for working in the full range of i/o conditions. 3modei mode setting. typically floating for dual-output use; tie to sgnd for parallel use. see tables 3 and 5 for details. when vsen2- is pulled within 700mv of vcc, the 2nd channel?s remote sensing amplifier is disabled. the mode pin, as well as the vsen2+ pin, determine relative phase-shift betw een the two channels and the clkout signal output. 18, 4 vmon1, vmon2 i/o remote sensing amplifier outputs. these pins are connected internally to ov/uv/pgood comparators, so they can?t float when the module works in multip hase operation. when vsen1-, vsen2- are pulled within 700mv of vcc, the corresponding remote sensing amplifier is disabled; the outp ut (vmon pin) is in high impedance. in this event, the vmon pins can be used as an additional monitor of the output voltage, with a resistor divider to protect the system against single point of failure. the default setting voltage is 0.6v. see table 3 for details. 5synci signal synchronization. an optional external resistor (r sync ) connected from this pin to sgnd increases oscillator switching frequency ( figure 34 and table 1 ). the internal default frequency is 350k hz with this pin floating. also, the internal oscillator can lock to an exte rnal frequency source or the clkout sign al from another ISL8240M. input voltage range for external source: 3v to 5v square wa ve. no capacitor is recommended on this pin. 6sgndpwr control signal ground. connect to pgnd under the module in the quiet inne r layer. make sure to have the single location for the connection between sgnd and pgnd to avoid noise coupling. see ? layout guide ? on page 25 . 7vccpwr 5v internal linear regulator output. voltage range: 3v to 5.6v. the decoupling ceramic capacitor for the vcc pin is recommended to be 4.7f. 14, 8 vin1, vin2 pwr power inputs. input voltage range: 4.5v to 20v. tie directly to the input rail. vin1 provides power to the internal linear drive circuitry. when the input is 4.5v to 5.5v, vin should be tied directly to vcc. 9, 13 pgnd pwr power ground. power ground pins for both input and output returns. 12, 10 phase1, phase2 pwr phase node. use for monitoring switching frequency. phase pins sh ould be floating or used for snubber connections. to achieve better thermal performance, the phase planes can also be used for heat removal with thermal vias connected to large inner layers. see ? layout guide ? on page 25. 11 nc - non-connection pin. this pin is floating with no connection inside. 15, 16 en/ff1, en/ff2 i/o enable and feed-forward control. tie a resistor divider to vin or use the syst em enable signal for this pin. the voltage turn-on threshold is 0.8v. with a voltage lower than th e threshold, the corresponding channel can be disabled independently. by connecting to vin with a resistor divider, the input voltage can be monitored for uvlo (undervoltage lockout) function. the voltage on each en/ff pin is also used to adjust the internal control loop gain independently to realize the feed-forward function. please set the en/ff betw een 1.25v to 5v. a 1nf capacitor is recommended on each en/ff pin. please see table 1 on page 19 to select a resistor divider and application details in ? en/ff turn on/off ? on page 21 . 17 clkout i/o clock out. provide the clock signal for the input synchronization signal of other ISL8240Ms. typically tied to vcc for dual-output use with 180 phase-shift. see tables 3 and 5 when using more than one is l8240m. when the module is in dual-output mode, the clock-out signal is disabled. by pr ogramming the voltage level of this clkout pin, the module can work for ddr/tracking or as two independent outputs with selectable phase-shift. see table 6 . 19 ishare o current sharing control. tie all ishare pins together when multiple modules are configured for current sharing and share a common current output. the ishare voltage repres ents the average current of all active and connected channels. a 470pf capacitor is recommended for each ishare pin for multiple phase applications. typically, the ishare pin should be floating for dual-output or single module application. 22, 26 vsen1+, vsen2+ i output voltage positive feedback. positive inputs of differen tial remote sense for the regulator. a resistor divider can be connected to this pin to program the output voltage. it is recommended to put the resistor divider close to the module and connect the kelvin sensing traces of vout an d vsen- to the sensing points of the load/processor; see figure 24 . the vsen2+ pin can be used to program the module operation conditions. see tables 3 and 5 for details. 23, 25 vout1, vout2 pwr power output. apply output load between these pins and pgnd pins. output voltage range: 0.6v to 2.5v. 24 pgood o power-good. provide open-drain power-good signal when the output is within 9% of the nominal output regulation point with 4% hysteresis (13%/9%) and soft-start complete. pgood monitors the outputs (vmon) of the internal differential amplifiers.
ISL8240M 7 fn8450.2 january 7, 2015 submit document feedback absolute maximum rating s thermal information input voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +25v driver bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v phase voltage, v phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +30v input, output or i/o control voltage . . . . . . . . . . . . . . . -0.3v to v cc + 0.3v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charge device model (tested per jesd22-c101c). . . . . . . . . . . . . . 750v latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) qfn package (notes 5, 6) . . . . . . . . . . . . . . 8.5 0.9 maximum storage temperature range . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to figure 44 recommended operating conditions input voltage, v in1 and v in2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 20.0v output voltage, v out1 and v out2 . . . . . . . . . . . . . . . . . . . . . . . 0.6v to 2.5v junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for ? jc , the ?case temp? location is the center of the phase exposed metal pad on the package underside. electrical specifications t a = +25c, v in = 12v, unless otherwise noted. boldface limits apply across the internal junction temperature range, -40c to +125c ( note 4 ). parameter symbol test conditions min ( note 7 ) typ ( note 8 ) max ( note 7 )units vcc supply current nominal supply v in current i q_vin v in = 20v; no load; en1 = en2 = high; v out1 = v out2 = 1.5v 140 ma v in1 = 20v; no load; en1 = high, en2 = low; v out1 = 1.5v 80 ma v in2 = 20v; no load; en1 = low, en2 = high; v out2 = 1.5v 76 ma v in1 = 12v; no load; en1 = high, en2 = high; v out1 = v out2 = 1.5v 159 ma v in = 4.5v; no load; en1 = en2 = high; v out1 = v out2 = 1.5v 188 ma v in1 = 4.5v; no load; en1 = high, en2 = low; v out1 = 1.5v 102 ma v in2 = 4.5v; no load; en1 = low, en2 = high; v out2 = 1.5v 94 ma internal linear regulator ( note 9 ) maximum current i pvcc v cc = 4v to 5.6v 250 ma saturated equivalent impedance r ldo p-channel mosfet (v in = 5v) 1 v cc voltage level v cc i vcc = 0ma 5.1 5.4 5.6 v power-on reset ( note 9 ) rising v cc threshold 0c to +75c 2.85 2.97 v -40c to +85c 2.85 3.05 v falling v cc threshold 2.65 2.75 v system soft-start delay t ss_dly after pll and v cc pors, and en above their thresholds 384 cycles enable ( note 9 ) turn-on threshold voltage 0.75 0.8 0.86 v hysteresis sink current i en_hys 23 30 35 a undervoltage lockout hysteresis v en_hys v en_rth = 10.6v; v en_fth = 9v, r up = 53.6k , r down = 5.23k 1.6 v sink current i en_sink v enff = 1v 15.4 ma sink impedance r en_sink i en_sink = 5ma, v enff = 1v 64 oscillator oscillator frequency f osc sync pin is open 350 khz total variation ( note 9 )v cc = 5v; -40c < t a < +85c -9 +9 %
ISL8240M 8 fn8450.2 january 7, 2015 submit document feedback frequency synchronization and phase lock loop (note 9) synchronization frequency v cc = 5v 350 700 khz pll locking time v cc = 5.4v, f sw = 500khz 130 s input signal duty cycle range 10 90 % pwm ( note 9 ) minimum pwm off time t min_off 310 345 410 ns current sampling blanking time t blanking 175 ns output characteristics output continuous current range i out(dc) v in = 12v, v out1 = 1.5v 020 a v in = 12v, v out2 = 1.5v 020 a v in = 12v, v out = 1.5v, in parallel mode 040 a line regulation accuracy ? v out / ? v in v in = 4.5v to 20v v out1 = 1.5v, i out1 = 0a 0.0065 % v out2 = 1.5v, i out2 = 0a 0.0065 % v in = 4.5v to 20v v out1 = 1.5v, i out1 = 20a 0.01 % v out2 = 1.5v, i out2 = 20a 0.01 % load regulation accuracy ? v out /v out v in = 5v, 2x47f ceramic capacitor and 1x330f poscap i out1 = 0a to 20a, v out1 = 1v 1 % i out2 = 0a to 20a, v out2 = 1v 1 % output ripple voltage ? v out v in = 12v, 4x100f +2x10f ceramic capacitor and 1x330f poscap i out1 = 0a, v out1 = 1.5v 16 mv p-p i out2 = 0a, v out2 = 1.5v 16 mv p-p i out1 = 20a, v out1 = 1.5v 21 mv p-p i out2 = 20a, v out2 = 1.5v 21 mv p-p dynamic characteristics voltage change for positive load step ? v out-dp current slew rate = 2.5a/s v in = 12v, v out = 1.5v, 4x100f + 2x10f ceramic capacitor and 1x330f poscap i out1 = 0a to 10a 100 mv p-p i out2 = 0a to 10a 100 mv p-p voltage change for negative load step ? v out-dn current slew rate = 2.5a/s v in = 12v, v out = 1.5v, 4x100f + 2x10f ceramic capacitor, and 1x330f poscap i out1 = 10a to 0a 80 mv p-p i out2 = 10a to 0a 80 mv p-p reference ( note 9 ) reference voltage (include error and differential amplifier offsets) v ref1 t a = -40c to +85c 0.5958 0.6 0.6042 v -0.7 0.7 % reference voltage (include error and differential amplifier offsets) v ref2 t a = -40c to +85c 0.5955 0.6 0.6057 v -0.75 0.95 % electrical specifications t a = +25c, v in = 12v, unless otherwise noted. boldface limits apply across the internal junction temperature range, -40c to +125c ( note 4 ). (continued) parameter symbol test conditions min ( note 7 ) typ ( note 8 ) max ( note 7 )units
ISL8240M 9 fn8450.2 january 7, 2015 submit document feedback differential amplifier ( note 9 ) dc gain ug_da unity gain amplifier 0 db unity gain bandwidth ugbw_da 5mhz vsen+ pin sourcing current i vsen+ 0.2 1 2.5 a maximum source current for current sharing i vsen1- vsen1- source current for current sharing when parallel multiple modules, each of which has its own voltage loop 350 a input impedance r vsen+_to _vsen- v vsen+ /i vsen+ , v vsen+ = 0.6v -600 k output voltage swing 0v cc - 1.8 v input common mode range -0.2 v cc - 1.8 v disable threshold v vsen- v mon1,2 = tri-state v cc - 0.4 v overcurrent protection ( note 9 ) channel overcurrent limit i limit1 v in = 12v, v out1 = 1.5v, r sync = 768k 24.5 a i limit2 v in = 12v, v out2 = 1.5v, r sync = 768k 24 a share pin oc threshold v oc_set v cc = 5v (comparator offset included) 1.16 1.20 1.22 v current share current share accuracy ? i/iout v in = 12v, v out = 1.5v i out = 40a, vsen2- = high 10 % power-good monitor ( note 9 ) undervoltage falling trip point v uvf percentage below reference point -15 -13 -11 % undervoltage rising hysteresis v uvr_hys percentage above uv trip point 4 % overvoltage rising trip point v ovr percentage above reference point 11 13 15 % overvoltage falling hysteresis v ovf_hys percentage below ov trip point 4 % pgood low output voltage i pgood = 2ma 0.35 v sinking impedance i pgood = 2ma 70 maximum sinking current v pgood < 0.8v 10 ma overvoltage protection ( note 9 ) ov latching-up trip point en/ff = ugate = latch low, lgate = high 118 120 122 % ov non-latching-up trip point en = low, ugate = low, lgate = high 113 % lgate release trip point en = low/high, ugate = low, lgate = low 87 % over-temperature protection ( note 9 ) over-temperature trip (controller junction temperature) 150 c over-temperature release threshold (controller junction temperature) 125 c notes: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. parameters with typ limits are not prod uction tested, unless otherwise specified. 9. parameters are 100% tested for internal ic prior to module assembly. electrical specifications t a = +25c, v in = 12v, unless otherwise noted. boldface limits apply across the internal junction temperature range, -40c to +125c ( note 4 ). (continued) parameter symbol test conditions min ( note 7 ) typ ( note 8 ) max ( note 7 )units
ISL8240M 10 fn8450.2 january 7, 2015 submit document feedback typical performance characteristics efficiency performance t a = +25c, if not specified, as shown in figure 23 with 2nd phase disabled. the efficiency equation is as follows: figure 3. efficiency vs load current (5v in ) figure 4. efficiency vs switching frequency at v in = 5v and i out = 18a for various output voltages figure 5. efficiency vs load current (12v in ) figure 6. efficiency vs switching frequency at v in = 12v and i out = 18a for various output voltages figure 7. efficiency vs load current (parallel single output, as shown in figure 24 at 5v in ) figure 8. efficiency vs switching frequency at v in = 5v (parallel single output, as shown in figure 24 ) and i out = 36a for various output voltages efficiency output power input power ----------------------------------------- p out p in --------------- - v out xi out ?? v in xi in ?? -------------------------------------- === 60 65 70 75 80 85 90 95 100 0 2 4 6 8 10 12 14 16 18 20 2.5v out 700khz 1.5v out 700khz 1.2v out 550khz 1v out 500khz 1.8v out 650khz load current (a) efficiency (%) 83 84 85 86 87 88 89 90 91 92 350 400 450 500 550 600 650 700 switching frequency (khz) efficiency (%) 2.5v out 1v out 1.8v out 1.2v out 1.5v out 55 60 65 70 75 80 85 90 95 02468101214161820 load current (a) efficiency (%) 2.5v out 700khz 1.5v out 600khz 1.2v out 550khz 1v out 500khz 1.8v out 650khz 82 83 84 85 86 87 88 89 90 91 350 400 450 500 550 600 650 700 switching frequency (khz) efficiency (%) 1.2v out 2.5v out 1v out 1.8v out 1.5v out 60 65 70 75 80 85 90 95 100 0 5 10 15 20 25 30 35 40 1.5v out 700khz 1.2v out 550khz 1v out 500khz load current (a) efficiency (%) 2.5v out 700khz 1.8v out 650khz 83 84 85 86 87 88 89 90 350 400 450 500 550 600 650 700 switching frequency (khz) efficiency (%) 1.2v out 1v out 1.8v out 1.5v out
ISL8240M 11 fn8450.2 january 7, 2015 submit document feedback figure 9. efficiency vs load current (parallel single output, as shown in figure 24 at 12v in ) figure 10. efficiency vs switching frequency at v in = 12v (parallel single output, as shown in figure 24 at 12v in ) and i out = 18a for various output voltages transient response performance v in = 12v current slew rate = 10a/s. t a = +25c, if not specified, as shown in figure 23 with 2nd phase disabled. figure 11. 1v out transient response, i out = 0a to 10a, f sw = 350khz, cout = 2x10f+7x100f ceramic capacitor, cff = 6.8nf figure 12. 1.5v out transient response, i out = 0a to 10a, f sw = 400khz, cout = 2x10f+7x100f ceramic capacitor, cff = 6.8nf figure 13. 1.8v out transient response, i out = 0a to 10a, f sw = 450khz, cout = 2x10f+7x100f ceramic capacitor, cff = 6.8nf figure 14. 2.5v out transient response, i out = 0a to 10a, f sw = 500khz, cout = 2x10f+7x100f ceramic capacitor, cff = 6.8nf typical performance characteristics (continued) 60 65 70 75 80 85 90 95 100 0 5 10 15 20 25 30 35 40 1.2v out 550khz 1v out 500khz load current (a) efficiency (%) 2.5v out 700khz 1.8v out 650khz 1.5v out 700khz 83 84 85 86 87 88 89 90 91 92 350 400 450 500 550 600 650 700 switching frequency (khz) efficiency (%) 1.2v out 2.5v out 1v out 1.8v out 1.5v out 100mv/div 100s/div 100mv/div 100s/div 100mv/div 100s/div 100mv/div 100s/div
ISL8240M 12 fn8450.2 january 7, 2015 submit document feedback transient response performance v in = 12v current slew rate = 10a/s. t a = +25c, if not specified, as shown in figure 23 with 2nd phase disabled. (continued) figure 15. 1v out dual phase single output transient response, i out = 0a to 20a, f sw = 350khz, cout = 330f poscap+10f+5x100f ceramic capacitor figure 16. 1.5v out dual phase single output transient response, i out = 0a to 20a, f sw = 400khz, cout = 330f poscap+10f+5x100f ceramic capacitor figure 17. 0.9v out four phase single output transient response, i out = 0a to 40a, f sw = 350khz, cout = 6x330f poscap+7x47f+4x100f ceramic capacitor figure 18. 1v out six phase single output transient response, i out = 0a to 60a, f sw = 350khz, cout = 6x330f poscap+7x47f+6x100f ceramic capacitor typical performance characteristics (continued) 100mv/div 100s/div 100mv/div 100s/div 100mv/div 50s/div 100mv/div 100s/div
ISL8240M 13 fn8450.2 january 7, 2015 submit document feedback start-up and short circuit performance v in = 12v, v out = 1.5v, cin = 1x330f, 3x22f/ceramic, cout = 330f poscap+1x10f+4x100f ceramic. t a = +25c, if not specified, as shown in figure 23 with 2nd phase disabled. figure 19. start-up at 0a figure 20. start-up at 20a figure 21. short circuit at 0a figure 22. short circuit at 20a typical performance characteristics (continued) 1ms/div v out 0.1a/div 0.5v/div i in 1ms/div v out 1a/div 0.5v/div i in 100s/div v out 1a/div 0.5v/div i in v out 1a/div 50s/div 0.5v/div i in
ISL8240M 14 fn8450.2 january 7, 2015 submit document feedback typical application circuits figure 23. dual outputs for 1.0v/20a and 1.5v/20a figure 24. parallel use for single 1.2v/40a output 1.0v at 20a 1.5v at 20a 4.5v to 20v vout2 vout1 vin r1* 1k r4* 665 r5* r2* 1.5k c1 cout1 r6* cout3 r3* 1k cin2 ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 1 14 8 15 16 7 17 3 19 5 20 2 23 22 21 25 26 18 4 12 10 24 69 *see table 4 on page 21 , resistors set on vsen+ and vsen- pins. 6x22f cout2 330f 4x100f 4x100f cout4 330f 4.7f see layout guide on page 25 for shorting sgnd to pgnd cff (optional) cff (optional) cin1 330f + + + *see table 1 on page 19 for r5/r6 values. 140k r sync 1.2v at 40a 4.5v to 20v vcc vout vin *cout cin2 r2 4.7f ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 r4* r3* r1 1k 1 14 8 15 16 7 17 3 19 5 20 2 23 22 21 25 26 18 4 12 10 24 69 5x22f 9x100f 470pf 2 size:1210 2 2200pf 2200pf optional snubbe r for noise attenuation. see figure 35, recommended layout , on page 26 . see layout guide on page 25 for shorting sgnd to pgnd 1k load kelvin remote sensing lines c1 c2 size:1210 cin1 330f + *see table 1 on page 19 for r3/r4 values. *the ISL8240M is internally compensated for stability for all ceramic capacitor applications. cff (optional) 174k r sync
ISL8240M 15 fn8450.2 january 7, 2015 submit document feedback figure 25. ddr/tracking use typical application circuits (continued) 2.5v 1.25v vddq/2 4.5v to 20v vddq vtt vddq vin c2 1nf ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 r6* r7 1k c1 4.7f r8 324 cout2 cin2 r5* cout1 1 14 8 15 16 7 17 3 19 5 20 2 23 22 21 25 26 18 4 12 10 24 69 *set the clkout voltage close to 0.61v. see details in functional description on page 22 5x22f 7x100f 7x100f r2 316 r1 1k r4 931 r3 1k cin1 330f + *see table 1 on page 19 for r5/r6 values. 100k r sync
ISL8240M 16 fn8450.2 january 7, 2015 submit document feedback figure 26. 4-phase paralleled at 1.0v/80a with 90 interleaving typical application circuits (continued) 1.0v/80a 4.5v to 20v pgood vcc vcc2 vcc1 vout1 vin cin2 5x22f r7 1.5k c5 470pf c1 4.7f cout3 4x100f r4* r5 3.3k ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sg nd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 cin2 5x22f ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 c2 4.7f r2 1.5k c4 470pf c3 470pf cout1 4x100f r3* r1 1k r6 1k vcc1 vcc2 cin1 2x470f + *see table 1 on page 19 for r3/r4 values. master phase slave slave slave cout2 2x330f + cout4 2x330f + 237k r sync r8 953 c6 22nf r9 953 c7 22nf
ISL8240M 17 fn8450.2 january 7, 2015 submit document feedback figure 27. 3-phase paralleled at 1.0v/50a and 1-phase at 2.5v/10a output with 90 interleaving typical application circuits (continued) 1.0v/50a 4.5v to 20v pgood 2.5v/10a vcc1 vcc2 vcc1 vcc vout1 vin vout2 r4* cout1 ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 cout5 cin1 cin2 1k c1 ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 r3* cout3 r11 1.5k r5 r7 100k c3 1 14 8 15 16 7 17 3 19 5 20 2 23 22 21 25 26 18 4 12 10 24 69 1 14 8 15 16 7 17 3 19 5 20 2 23 22 21 25 26 18 4 12 10 24 69 5x22f 4.7f 5x22f 4x100f 2x100f 7x100f r2 1.5k r1 1k 3.3k vcc1 4.7f c2 470pf r9 316 r8 1k r10 c4 470pf vcc2 2x470f + master phase *see table 1 on page 19 for r3/r4 values. slave slave cout2 2x330f + cout4 330f + r6 953 c5 22nf
ISL8240M 18 fn8450.2 january 7, 2015 submit document feedback figure 28. six-phase 120a 1.0v output circuit typical application circuits (continued) vcc2 2x470f + 1.0v/120a 4.5v to 20v pgood vcc1 vcc3 vcc2 vcc1 vout vin c1 c5 cin3 ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 c2 cout2 cin2 cout3 ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 r3* r6* 500 r4* r7* 750 r5 cin1 cout1 ISL8240M vin1 sync clkout vcc ishare vsen1+ vsen1- en/ff1 en/ff2 vsen2- vsen2+ sgnd pgnd vout1 vout2 phase1 phase2 mode vmon2 comp1 pgood comp2 vmon1 vin2 1 14 8 15 16 7 17 3 19 5 20 2 23 22 21 25 26 18 4 12 10 24 69 1 14 8 15 16 7 17 3 19 5 20 2 23 22 21 25 26 18 4 12 10 24 69 1 14 8 15 16 7 17 3 19 5 20 2 23 22 21 25 26 18 4 12 10 24 69 *keep r6/r7 the same pin can have seperate resistor divider to 4.7f 4x22f 4x22f 4x22f 4.7f 3x100f 3x100f 3x100f 3.3k 4.7f c8 470pf 470pf 470pf r2 1.5k r1 1k 470pf c3 ratio as r1/r2. each vmon monitor the output voltage. vcc1 c4 vcc3 c7 470pf c6 master phase *see table 1 on page 19 for r3/r4 values. slave slave slave slave slave cout4 4x330f + 237k ? r sync
ISL8240M 19 fn8450.2 january 7, 2015 submit document feedback table 1. ISL8240M design guide matrix (refer to figure 23 ) case v in (v) v out (v) r2 or r4 ( ) cin1 (bulk) (f) ( note 10 ) cin2 (ceramic) (f) cout1 (ceramic) (f) cout2 (bulk) cff (nf) en/ff (k ) r5/r6 ( note 11 ) freq. (khz) r sync (k ) load (a) ( note 12 ) 1 5 1 1.5k 1x330 1x100 4x100 1x330f none 6.04/3.01 500 237 20 2 5 1 1.5k 1x330 1x100 7x100 none 6.8 6.04/3.01 500 237 20 3 12 1 1.5k 1x330 3x22 4x100 1x330f none 6.04/1.50 500 237 20 4 12 1 1.5k 1x330 3x22 7x100 none 6.8 6.04/1.50 500 237 20 5 5 1.2 1.0k 1x330 1x100 4x100 1x330f none 6.04/3.01 550 174 20 6 5 1.2 1.0k 1x330 1x100 7x100 none 6.8 6.04/3.01 550 174 20 7 12 1.2 1.0k 1x330 3x22 4x100 1x330f none 6.04/1.50 550 174 20 8 12 1.2 1.0k 1x330 3x22 7x100 none 6.8 6.04/1.50 550 174 20 9 20 1.2 1.0k 1x330 3x22 4x100 1x330f none 6.04/1.50 550 174 19 10 20 1.2 1.0k 1x330 3x22 7x100 none 6.8 6.04/1.50 550 174 19 11 5 1.5 665 1x330 1x100 4x100 1x330f none 6.04/3.01 700 100 18 12 5 1.5 665 1x330 1x100 7x100 none 6.8 6.04/3.01 700 100 18 13 12 1.5 665 1x330 3x22 4x100 1x330f none 6.04/1.50 600 140 19 14 12 1.5 665 1x330 3x22 7x100 none 6.8 6.04/1.50 600 140 19 15 20 1.5 665 1x330 3x22 4x100 1x330f none 6.04/1.50 600 140 18 16 20 1.5 665 1x330 3x22 7x100 none 6.8 6.04/1.50 600 140 18 17 5 2.5 316 1x330 1x100 4x100 1x330f none 6.04/3.01 700 100 18 18 5 2.5 316 1x330 1x100 7x100 none 6.8 6.04/3.01 700 100 18 19 12 2.5 316 1x330 3x22 4x100 1x330f none 6.04/1.50 700 100 18 20 12 2.5 316 1x330 3x22 7x100 none 6.8 6.04/1.50 700 100 18 21 20 2.5 316 1x330 3x22 4x100 1x330f none 6.04/1.50 700 100 16 22 20 2.5 316 1x330 3x22 7x100 none 6.8 6.04/1.50 700 100 16 notes: 10. cin bulk capacitor is optional only for decoupling noise due to the long input cable. cin2 and cout1 ceramic capacitors are listed for one phase only. please increase the capacitor quantity for dual-phase operations. 11. en/ff resistor divider is ti ed directly to vin. the resistors listed here ar e for two channels' en/ff pins tied together. if the separate resistor divider is used for each channel, the resistor value needs to be doubled. 12. max load current listed in the table is for conditions at +25c and no air flow on a typical intersil 4-layer evaluation boa rd. table 2. recommended i/o capacitor in table 1 vendor value part number tdk, input and output ceramic 100f, 6.3v, 1210 c3225x5r0j107m murata, input and output cerami c 100f, 6.3v, 1210 grm32er60j107m avx, input and output ceramic 100f, 6.3v, 1210 12106d107mat2a murata, input ceramic 22f, 25v, 1210 grm32er61e226ke15l taiyo yuden, input ceramic 22f, 25v, 1210 tmk325bj226mm-t avx, input ceramic 22f, 25v, 1210 12103d226kat2a panasonic poscap, output bulk 330f, 6.3v 6tpf330m9l panasonic smt, input bulk 330f, 25v eevha1e331up
ISL8240M 20 fn8450.2 january 7, 2015 submit document feedback table 3. ISL8240M operation modes 1st module (i = input; o = output; i/o = inpu t and output, bidirection) modes of operation output (see description for details) operation mode of 2 nd module operation mode of 3 rd module mode en1/ff1 (i) en2/ff2 (i) vsen2- (i) mode (i) vsen2+ (i) clkout/refin wrt 1 st (i or o) vmon2 ( note 14 ) vmon1 of 2 nd module ( note 14 ) 2 nd channel wrt 1 st (o) ( note 13 ) 10 0 - - - ---- --disabled 2a 0 1 active active active - active - vmon1 = vmon2 to keep pgood valid --single phase 2b 1 0 - - - - - - vmon1 = vmon2 to keep pgood valid --single phase 3a 1 1 62% of v cc (i) active - 180 - - dual regulator 41 112) notes: 13. ?2 nd channel wrt 1st? means ?second channel with respect to first;? in other words, channel 2 lags channel 1 by the degrees specifi ed in this column. for example, 90 means channel 2 lags channel 1 by 90; -60 means channel 2 leads channel 1 by 60. 14. ?vmon1? means that the pin is tied to the vmon1 pin of the same module. ?divider? means that there is a resistor divider from vout to sgnd; refer to figure 28 . ?953 //22nf? means that there is a 953 resistor in parallel with a 22nf capacitor connecting the pin to sgnd; refer to figure 26 .
ISL8240M 21 fn8450.2 january 7, 2015 submit document feedback application information programming the output voltage the ISL8240M has an internal 0.6v 0.7% reference voltage. programming the output voltage requires a resistor divider (r1 and r2) between the vout, vsen+, and vsen- pins, as shown in figure 23 on page 14 . please note that the output voltage accuracy is also dependent on the resistor accuracy of r1 and r2. the user needs to select a hi gh accuracy resistor (i.e., 0.5%) in order to achieve the overall output accuracy. the output voltage can be calculated as shown in equation 1 : note: it is recommended to use a 1k value for the top resistor, r1. the value of the bottom resistor for different output voltages is shown in table 4 . at higher output voltage, the inductor ripple increases, which makes both output ripple and inductor power loss higher. refer to figure 34 on page 24 to choose r sync which adjusts the switching frequency. selection of input capacitor selection of the input filter capacitor is based on how much ripple the supply can tolerate on the dc input line. the larger the capacitor, the less ripple expected, however, consideration should be given to the higher surge current during power-up. the ISL8240M provides a soft-start function that controls and limits the current surge. a combination of bulk capacitors and low equivalent series resistance (esr) ceramic capacitors are recommended as input capacitors. the minimum value of the input ceramic capacitors can be calculated as shown in equation 2 : where: ?c in(cer, min) is the minimum required input ceramic capacitance (f) ?i o is the output current (a) ? d is the duty cycle ?v p-p is the allowable peak-to-peak voltage (v) ?f sw is the switching frequency (hz) the low equivalent series resistance (esr) ceramic capacitance is recommended to decouple betw een the vin and pgnd of each channel. see table 2 for some recommended capacitors. this capacitance reduces voltage ringing created by the switching current across parasitic circui t elements. all these ceramic capacitors should be placed as closely as possible to the module pins. the estimated rms current should be considered in choosing ceramic capacitors. each 10f x5r or x7r ceramic capacitor is typically good for 2a to 3a of rms ripple current. refer to the capacitor vendor to check the rms current ratings. in a typical 15a output application for one channel, if the duty cycle is 0.5, it needs at least three 10f x5r or x7r ceramic input capacitors. selection of output capacitors the ISL8240M is designed for low-output voltage ripple. the output voltage ripple an d transient requirements can be met with bulk output capacitors (cout) that have adequately low esr. cout can be a low esr tantalum capacitor, a low esr polymer capacitor or a ceramic capacitor. the typical capacitance is 330f, and decoupling ceramic output capacitors are used for each phase. see tables 1 and 2 for more capacitor information. internally optimized loop comp ensation provides sufficient stability margins for all ceramic capacitor applications, with a recommended total value of 700f per phase. additional output filtering may be needed if further reduction of output ripple or dynamic transient spike is required. en/ff turn on/off each output of the ISL8240M can be turned on/off independently through the en/ff pi ns. for parallel use, tie all en/ff pins together. since this pi n has the feed-forward function, the voltage on this pin can active ly adjust the loop gain to be constant for variable input voltage. please refer to table 1 on page 19 to select the resistor divider for commonly used conditions. otherwise, use the following procedures to finish the en/ff design: 1. a resistor divider from v in to gnd is recommended to set the en/ff voltage between 1.25v to 5.0v. the resistor divider ratio is recommended to be between 3/1 to 4/1 with a resistor divider at 7.15k /2.05k . 2. check en turn-on hysteresis (recommend v en_hys >0.3v) : where: ?r up is the top resistor of the resistor divider ? n is the total number of the en/ff pins tied to the resistor divider table 4. value of bottom resistor for different output voltages (v out vs r2) r1 ( ) v out (v) r2 ( ) 1k 0.6 open 1k 0.8 3.01k 1k 1.0 1.50k 1k 1.2 1.00k 1k 1.5 665 1k 1.8 499 1k 2.0 422 1k 2.5 316 v out 0.6 1 r1 r2 ------- - + ?? ?? ? = (eq. 1) c in cer min ? ?? i o d1 d C ?? ? v p-p f sw ? ---------------------------------- - = (eq. 2) i in rms ?? io d 1 d C ?? ? -------------------------------- - = (eq. 3) v en hys C nr ? up 3x10 5 C ? = (eq. 4)
ISL8240M 22 fn8450.2 january 7, 2015 submit document feedback 3. set the maximum current flowing through the top pull-up resistor r up to below 7ma (considering en/ff is pulled to ground (v en/ff = 0)). refer to figure 27 on page 17 ; a 3.01k /1k resistor is used to allow for the input voltage from 5v to 20v operation. in addition, the maximum current flowing through r5 is 6.6ma (<7ma). 4. if the en/ff is controlled by system en signal instead of the input voltage, we recommend setting the fixed en/ff voltage to about 1/3.5 of the input voltage. if the input voltage is 12v, a 3.3v system en signal can be tied to en/ff pin directly. 5. if the input voltage is below 5.5v, it is recommended to have en/ff voltage >1.5v to have better stability. the input voltage can be directly tied to the vcc pin to disable the internal ldo. 6. a 1nf capacitor is recommended on the en/ff pin to avoid the noise injecting into the feed-forward loop. thermal considerations the ISL8240M qfn package offers typical junction to ambient thermal resistance ? ja of approximately 8.5c/w at natural convection (~5.0c/w at 400lfm) with a typical 4-layer pcb. therefore, use equation 5 to estimate the module junction temperature: where: ?t junction is the module internal maximum temperature (c) ?t ambient is the system ambient temperature (c) ? p is the total power loss of the module package (w) ? ? ja is the thermal resistance of module junction to ambient if the calculated temperature, t junction , is over the required design target, the extra cooling sc heme is required. please refer to ? current derating ? on page 26 for adding air flow. functional description initialization initially, the power-on reset (por ) circuits continuously monitor bias voltages (v cc ) and voltage at the en/ff pin. the por function initiates soft-start operation 384 clock cycles after: (1) the en pin voltage is pulled above 0.8v, (2) all input supplies exceed their por thresholds, and (3) the pll locking time expires. the enable pin ca n be used as a voltage monitor and to set the desired hysteresis, with an internal 30a sinking current going through an external resistor divider. the sinking current is disengaged after the system is enabled. this feature is specially designed for applications that require higher input rail por for better undervoltage protection. for example, in 12v applications, r up = 53.6k and r down = 5.23k sets the turn-on threshold (v en_rth ) to 10.6v and the turn-off threshold (v en_fth ) to 9v, with 1.6v hysteresis (v en_hys ). during shutdown or fault conditions, soft-start is quickly reset, and the gate driver immediately changes state (<100ns) when input drops below por. enable and voltage feed-forward voltage applied to the en/ff pin is fed to adjust the sawtooth amplitude of the channel. sawtooth amplitude is set to 1.25 times the corresponding ff voltage when the module is enabled. this configuration helps maintain a co nstant gain. this configuration also helps maintain input voltage to achieve optimum loop response over a wide input voltage range. a 384-cycle delay is added after the system reac hes its rising por and prior to soft-start. the rc timing at the ff pin should be small enough to ensure that the input bus reaches its static state and that the internal ramp circuitr y stabilizes before soft-start. a large rc could cause the internal ramp amplitude not to synchronize with the input bus volt age during output start-up or when recovering from faults. a 1nf capacitor is recommended as a starting value for typical applications. in a multi-module system, with the en pins wired together, all modules can immediately turn off, at one time, when a fault condition occurs in one or more modules. a fault pulls the en pin low, disabling all modules, and does not create current bounce; thus, no single channel is overstressed when a fault occurs. because the en pins are pulled do wn under fault conditions, the pull-up resistor (r up ) should be scaled to sink no more than 7ma current from the en pin. essentially, the en pins cannot be directly connected to vcc. t junction p ? ja ? t ambient + = (eq. 5) figure 29. simplified enable and voltage feed-forward circuit 0.8v i en_hys = 30a r up r down soft-start r down r up v 2 en_ref v en_fth v en_ref C -------------------------------------------------------------- - = v en_fth v en_rth v en_hys C = vin en ov, ot, oc, and pll locking faults r up v en_hys i en_hys ---------------------------- - = on/off 384 cycles clock
ISL8240M 23 fn8450.2 january 7, 2015 submit document feedback soft-start the ISL8240M has an internal, digital, precharged soft-start circuitry ( figures 30 through 32 ). the circuitry has a rise time inversely proportional to the switching frequency. rise time is determined by a digital counter that increments with every pulse of the phase clock. the full soft-start time from 0v to 0.6v can be estimated as shown in equation 6 . the typical soft-start time is ~2.5ms. the ISL8240M is able to work under a precharged output. the pwm outputs do not feed to the drivers until the first pwm pulse is seen. the low-side mosfet is on for the first clock cycle, to provide charge for the bootstrap capacitor. if the precharged output voltage is greater than the final target level but less than the 113% set point, switching does not start until the output voltage is reduced to the target voltage and the first pwm pulse is generated. the maximum allowable precharged level is 113%. if the precharged level is above 113% but below 120%, the output hiccups between 113% (lgate turns on) and 87% (lgate turns off), while en is pulled low. if the precharged load voltage is above 120% of the targeted output voltage, then the controller is latched off and cannot power up. power-good power-good comparators monitor voltage on the vmon pin. trip points are shown in figure 33 . pgood is not asserted until the soft-start cycle is complete. pgood pulls low upon both ens disabling it or when the vmon voltage is out of the threshold window. pgood does not pull low until the fault presents for three consecutive clock cycles. uv indication is not enabled until the end of soft-start. in a uv event, if the output drops below -13% of the target level due to a reason other than ov, oc, ot, or pll faults (cases when en is not pulled low), pgood is pulled low. current share in parallel operations, the share bus voltages (i share ) of different modules must tie together. the ishare pin voltage is set by an internal resistor and represents the average current of all active modules. the average cu rrent signal is compared with the local module current, and the current share error signal is fed into the current correction bloc k to adjust each module?s pwm pulse accordingly. the current sh are function prov ides at least 10% overall accuracy between modules. the current share bus works for up to 12 phases without requiring an external clock. a 470pf ~1nf capacitor is recommended for each ishare pin. in current sharing scheme, all sl ave channels have the feedback loops disabled with the vsen- pin tied to vcc. the master channel can control all modules wi th comp and ishare pins tied together. for phase-shift setting, all vmon pins of slave channels are needed to set 0.6v for monitoring use only. typically, the slaved vmon pins can be tied together with a resistor divider to vout. however, if the mode pin is tied to vcc for mode setting, the related vmon2 pin is needed to tie to sgnd with a 953 resistor and a 22nf capacitor, as shown in figure 27 on page 17 . t ss 1280 f sw ------------ - = (eq. 6) v out target voltage 0.0v t ss 1280 f sw ------------ - = first pwm pulse -100mv t ss_dly 384 f sw ----------- - = figure 30. soft-start with v out = 0v ss settling at vref + 100mv init. v out vout target voltage first pwm pulse -100mv ss settling at vref + 100mv figure 31. soft-start with v out < target voltage ov = 113% v out target voltage first pwm pulse figure 32. soft-start with v out below 113% but above final target voltage figure 33. power-good threshold window -13% -9% v ref +9% +13% vmon1, 2 channel 2 uv/ov end of ss1 and pgood channel 1 uv/ov end of ss2 +20% pgood pgood latch off ss1_period and ss2_period after 120% ov or
ISL8240M 24 fn8450.2 january 7, 2015 submit document feedback if there are multiple modules paralleled with the mode pins tied to vcc, each vmon2 pin of the slave modules needs to have a 953 resistor to gnd while all vmon1 pins of the slave modules can be tied together with a resist or divider from vout to gnd, as shown in figure 28 on page 18 . also see table 3 on page 20 for vmon settings. because of the typical 5.4v vcc and the internal 7.5k resistor between mode pin and vmon2 pin, the 953 resistor maintains vmon2 pin voltage close to 0.6v, thus output ovp/uvp (caused by vmon2 voltage too high or too low) will not be falsely triggered due to part to part variation at mass production. the 22nf capacitor is used to avoid output uvp/ovp triggered during input start-up. overvoltage protection (ovp) the overvoltage (ov) protection indication circuitry monitors voltage on the vmon pin. ov protection is active from the beginning of soft-start. an ov condition (>120%) would latch the ic off. in this condition, the high-side mosfet (q1 or q3) latches off permanently. the low-side mosfet (q2 or q4) turns on immediately at the time of ov trip and then turns off permanently after the output vo ltage drops below 87%. en and pgood are also latched low in an ov event. the latch condition can be reset only by recycling v cc . there is another non-latch ov protection (113% of target level). when en is low and output is over 113% ov, the low-side mosfet turns on until output drops below 87%. this action protects the power trains when even a single channel of a multi-module system detects ov. the low-side mosfet always turns on when en = low and the output voltage rises above 113% (all en pins are tied together) and turns off after the output drops below 87%. thus, in a high phase count application (multi-module mode), all cascaded modules can latch off simultaneously via the en pins (en pins are tied together in multi-phase mode). each channel shares the same sink current to reduce stress an d eliminate bouncing among phases. over-temperature protection (otp) when the junction temperature of the internal controller is greater than +150c (typically), th e en pin is pulled low to inform other cascaded channels via their en pins. all connected ens stay low and then release after the module?s junction temperature drops below +125c (typically), a +25c hysteresis (typically). overcurrent protection (ocp) the ocp maximum load current level is set to about 24a for each channel, but the oc trip point can vary, due mainly to mosfet r ds(on) variations (over process, current, and temperature). the ocp can be increased by increasing the switching frequency since the inductor ripple is reduced. however, the module efficiency drops accordingly with more switching loss. when ocp is triggered, the controller pulls en low immediately to turn off all switches. the ocp function is enabled at st art-up and has a 7-cycle delay before it triggers. in multi-module operation, ishare pins can be connected to create v ishare , which represents the average current of all active channels. total system currents are compared with a precision threshold to determine the overcurrent condition. each channel also has an additional overcurrent set point with a 7-cycle delay. this scheme helps protect modules from damage in multi-module mode by having each module carry less current than the set point. for overload and hard short cond itions, overcurrent protection reduces the regulator rms output current to much less than full load by putting the controller into hiccup mode. a delay equal to three soft-start intervals is entered to allow time to clear the disturbance. after the delay time, the controller initiates a soft-start interval. if the output voltage comes up and returns to regulation, pgood transitions high . if the oc trip is exceeded during the soft-start interval, the controller pulls en low again. the pgood signal remains low, and the so ft-start interval is allowed to expire. another soft-start interval is initiated after the delay interval. if an overcurrent trip occurs again, this same cycle repeats until the fault is removed. since the output voltage may trigger the ovp if the output current changes too fast, the module can go into latch-off mode. in this case, th e module needs to be restarted. frequency synchronization and phase lock loop the sync pin has two primary capabilities: fixed frequency operation and synchronized frequency operation. the ISL8240M has an internally set fixed frequency of 350khz. by tying a resistor (r sync ) to sgnd from the sync pin, the switching frequency can be set to higher than 350khz. to increase the switching frequency, select an externally connected resistor, r sync , from sync to sgnd according to t he frequency setting curve shown in figure 34 . see table 1 on page 19 for r sync at commonly used frequency. connecting the sync pin to an external square-pulse waveform (such as the clkout signal, ty pically 50% duty cycle from another ISL8240M) synchronizes the ISL8240M switching frequency to the fundamental frequency of the input waveform. the synchronized frequency can be from 350khz to 700khz. the applied square-pulse recommended high level voltage range is 3v to v cc +0.3v. the frequency synchronization feature synchronizes the leading edge of the clkout signal with the falling edge of channel 1?s pwm signal. clkout is not available until pll locks. no capacitor is recommended on the sync pin. 0 100 200 300 400 500 600 700 800 400 450 500 550 600 650 700 switching frequency (khz) figure 34. r sync vs switching frequency r sync (k)
ISL8240M 25 fn8450.2 january 7, 2015 submit document feedback for 18a or less load current (or 36a for parallel single output configuration), the ISL8240M's efficiency can be improved by adjusting the switching frequency. please refer to figures 4 , 6 , 8 and 10 for the efficiency at different switching frequencies at various output voltages. for higher than 18a load current (or 36a for parallel single output configuration), please refer to table 1 on page 19 for the recommended switching frequencies for various conditions locking time is typically 130s for f sw = 500khz. en is not released for a soft-start cycle unti l sync is stabilized and pll is locking. connecting all en pins together in a multiphase configuration is recommended. loss of a synchronization signal for 13 clock cycles causes the module to be disabled until pll returns locking, at which point a soft-start cycle is initiated and no rmal operation resumes. holding sync low disables the module. please note that the quick change of the synchronization signal can cause module shutdown. tracking function if clkout is less than 800mv, an external soft-start ramp (0.6v) can be in parallel with the channe l 2 internal soft-start ramp for tracking applications. therefore, the output voltage of channel 2 can track the output voltage of channel 1. the tracking function can be applied to a typical double data rate ( ddr) memory application, as shown in figure 25 on page 15 . the output voltage (typical vtt output) of channel 2 tracks with the input voltage [typical vddq/(1+k) from channel 1] at the clkout pin. as for the external input signal and the internal reference signal (ramp and 0.6v), the one with the lowest voltage is used as the reference for comparing with the fb signal. in ddr configuration, vtt channel should start up later, after its internal soft-start ramp, such that vtt tracks the voltage on the clkout pin derive d from vddq. this configuration can be achieved by adding more filtering at en/ff1 than at en/ff2. it is recommended to scale the target clkout voltage to 0.612v (2% above 0.6v reference) with an external resistor divider from vddq. after start-up, the internal reference takes over to maintain the good regulation of vtt. the resistor divider ratio k of r7/r8 in figure 20 is based on the feedback divider of vddq (r1 and r2 values) and the 0.612v target clkout voltage as shown in equation 7 : mode programming ISL8240M can be programmed for dual-output, paralleled single-output or mixed outputs (channel 1 in parallel and channel 2 in dual-output). with multiple ISL8240Ms, up to 6 modules using its internal cascaded clock signal control, the modules can supply large current up to 240a. for complete operation, please refer to table 3 on page 20 . commonly used settings are listed in table 5 . when the module is in the dual-output condition, depending upon the voltage level at clkout (which is set by the vcc resistor divider output), ISL8240M operates with phase shifted as the clkout voltage shown in table 6 . the phase shift is latched as v cc rises above por; it cannot be changed on the fly. layout guide to achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary ( figure 35 ). ? vout1, vout2, phase1, phase2, pgnd, vin1 and vin2 should have large, solid planes. place enough thermal vias to connect the power planes in different layers under or around the module. ? place high-frequency ceramic capacitors between vin, vout, and pgnd, as closely to the mo dule as possible in order to minimize high-frequency noise. ? use remote sensed traces to the regulation point to achieve tight output voltage regulation , and keep the sensing traces close to each other in parallel. ? phase1 and phase2 pads are sw itching nodes that generate switching noise. keep these pads under the module. for noise-sensitive applications, it is recommended to keep phase pads only on the top and inner layers of the pcb. also, do not place phase pads exposed to the outside on the bottom layer of the pcb. ? avoid routing any noise-sensitive signal traces, such as the vsen+, vsen-, ishare, comp an d vmon sensing points, near the phase pins. ? use a separated sgnd ground copper area for components connected to signal ground pins. connect sgnd to pgnd with multiple vias underneath the unit in one location to avoid the noise coupling, as shown in figure 35 . don't ground vias surrounded by the noisy planes of vin, phase and vout. for dual output applications, the sg nd to pgnd vias are preferred to be as close as possible to sgnd pin. k r7 r8 ------- - 1r1r2 ? + ?? 1.02 ---------------------------------- 1 C == (eq. 7) table 5. phase-shift setting operation phase-shift between phases vsen2- vsen2+ clkout mode dual output ( figure 23 ) 180 n/c n/c vcc n/c 40a ( figure 24 ) 180 vcc n/c n/c sgnd 80a ( figure 26 ) 90 vcc vcc n/c vcc 120a ( figure 28 ) 60 vcc n/c n/c sgnd table 6. clkout to program phase shift at dual-output clkout voltage setting phase for clkout wrt channel 1 recommended clkout voltage <29% of v cc -60 15% v cc 29% to 45% of v cc 0 37% v cc 45% to 62% of v cc 90 53% v cc 62% of v cc 180 v cc
ISL8240M 26 fn8450.2 january 7, 2015 submit document feedback ? optional snubbers can be put on the bottom side of the board layout, connecting the phase to pgnd planes, as shown in figure 35 . current derating experimental power loss curves ( figures 36 and 37 ), along with ? ja from thermal modeling analysis, can be used to evaluate the thermal consideration for the module. derating curves are derived from the maximum power allowed while maintaining temperature below the maximum junction temperature of +120c ( figures 38 through 43 ). the maximum +120c junction temperature is considered for the module to load the current consistently and it prov ides the 5c margin of safety from the rated junction temperature of +125c. if necessary, customers can adjust the margin of safety according to the real applications. all derating curves are obtained from the tests on the ISL8240Meval4z evaluation board. in the actual application, other heat sources and design margins should be considered. package description the ISL8240M is integrated into a quad flat no-lead package (qfn). this package has such advantages as good thermal and electrical conductivity, low weight, and small size. the qfn package is applicable for surfac e mounting technology and is becoming more common in the in dustry. the ISL8240M contains several types of devices, incl uding resistors, capacitors, inductors, and control ics. the ISL8240M is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper lead frame and multi-component assembly are over-molded with polymer mold compound to protect these devices. the package outline, typical pcb layout pattern, and typical stencil pattern design are shown in the l26.17x17 package outline drawing on page 31 . figure 44 shows typical reflow profile parameters. these guidelines are general design rules. users can modify parameters according to specific applications. pcb layout pattern design the bottom of ISL8240M is a lead-frame footprint, which is attached to the pcb by surface mounting. the pcb layout pattern is shown in the l26.17x17 package outline drawing on page 31 . the pcb layout pattern is essentially 1:1 with the qfn exposed pad and the i/o termination dime nsions, except that the pcb lands are slightly longer than the qfn terminations by about 0.2mm (0.4mm max). this extensio n allows for solder filleting around the package periphery an d ensures a more complete and inspectable solder joint. the th ermal lands on the pcb layout should match 1:1 with the package exposed die pads. thermal vias a grid of 1.0mm to 1.2mm pitched thermal vias, which drops down and connects to buried copper planes, should be placed under the thermal land. the vias should be about 0.3mm to 0.33mm in diameter, with the barrel plated to about 2.0 ounce copper. although adding more vias (by decreasing pitch) improves thermal performance, it also diminishes results as more vias are added. use only as many vias as are needed for the thermal land size and as your board design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2mil to 3m il) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joins. the stencil aperture size to land size ratio should typically be 1:1. aperture width may be reduced slightly to help prevent solder bridging between adjacent i/o lands. to reduce solder paste volume on the larger thermal lands, an array of smaller apertures inst ead of one large aperture is recommended. the stencil printing area should cover 50% to 80% of the pcb layout pattern. a typical solder stencil pattern is shown in the l26.17x17 package outline drawing on page 31 . the gap width between pads is 0.6mm. consider the symmetry of the whole stencil pattern when designing the pads. a laser-cut, stainless-steel stencil with electropolished trapezoidal walls is recommended. electropolishing smooths the aperture walls, resulting in reduced surface friction and better paste release, which reduces void s. using a trapezoidal section aperture (tsa) also promotes paste release and forms a brick-like paste deposit, whic h assists in firm component placement. a 0.1mm to 0.15mm stencil thickness is recommended for this large-pitch (1.0mm) qfn. kelvin connections for the v sens lines cin2 cin1 cout1 cout2 pgnd vout1 vout2 phase1 phase2 pgnd vin2 vin1 sgnd pgnd kelvin connections for the v sens lines + - + - pin 1 r3 r4 r1 r2 to load to load figure 35. recommended layout optional snubber optional snubber
ISL8240M 27 fn8450.2 january 7, 2015 submit document feedback power loss curves figure 36. power loss curves of 5v in figure 37. power loss curves of 12v in 0 2 4 6 8 10 0 5 10 15 20 25 30 35 40 power loss (w) load current (a) 12 5v in to 1v out 350khz 5v in to 1.5v out 400khz 5v in to 2.5v out 500khz 0 2 4 6 8 10 0 5 10 15 20 25 30 35 40 power loss (w) 12 load current (a) 12v in to 1v out 350khz 12v in to 1.5v out 450khz 12v in to 2.5v out 500khz derating curves all of the following curves were plotted at t j = +120c. figure 38. derating curve 5v in to 1v out figure 39. derating curve 12v in to 1v out figure 40. derating curve 5v in to 1.5v out figure 41. derating curve 12v in to 1.5v out 0 5 10 15 20 25 30 35 40 25 35 45 55 65 75 85 95 105 115 125 5v in 1v out 350khz load current (a) 0lfm 200lfm 400lfm temperature (c) 0 5 10 15 20 25 30 35 40 25 35 45 55 65 75 85 95 105 115 125 12v in 1v out 350khz load current (a) temperature (c) 0lfm 200lfm 400lfm 0 5 10 15 20 25 30 35 40 25 35 45 55 65 75 85 95 105 115 125 load current (a) temperature (c) 5v in 1.5v out 400khz 0lfm 200lfm 400lfm 0 5 10 15 20 25 30 35 40 25 35 45 55 65 75 85 95 105 115 125 load current (a) temperature (c) 12v in 1.5v out 400khz 0lfm 200lfm 400lfm
ISL8240M 28 fn8450.2 january 7, 2015 submit document feedback reflow parameters due to the low mount height of th e qfn, "no clean" type 3 solder paste, per ansi/j-std-005, is re commended. nitrogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the qfn. the profile given in figure 44 is provided as a guideline to customize for varying manufacturing practices and applications. figure 42. derating curve 5v in to 2.5v out figure 43. derating curve 12v in to 2.5v out derating curves all of the following curves were plotted at t j = +120c. (continued) 0 5 10 15 20 25 30 35 40 0 20 40 60 80 100 120 140 load current (a) temperature (c) 5v in 2.5v out 500khz 0lfm 200lfm 400lfm 0 5 10 15 20 25 30 35 40 25 35 45 55 65 75 85 95 105 115 125 load current (a) temperature (c) 12v in 2.5v out 500khz 0lfm 200lfm 400lfm figure 44. typical reflow profile 0300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) slow ramp (3c/s max) and soak from +100c to +180c for 90s~120s ramp rate ? 1.5c from +70c to +90c peak temperature +230c~+245c; typically 60s-70s above +220c keep less than 30s within 5c of peak temp.
ISL8240M 29 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8450.2 january 7, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change january 7, 2015 fn8450.2 on page 7, electrical specifications table, vcc voltage level updated min from 5.15v to 5.1v and max from 5.95v to 5.6v. on page 8, electrical specifications table, vref1 and vref 2, added absolute values for min and max corresponding to the percentages. on page 16, figure 26, r8 value changed from 1k to 953 , added a capacitor c6, value of 22nf, in parallel with r8, r9 value changed from 1k to 953 , added a capacitor c7, value of 22nf, in parallel with r9. on page 17, figure 27, r6 value changed from 1k to 953 , added a capacitor c5, value of 22nf, in parallel with r6. on page 20, table 3, updated vmon2 from 1k to "953 //22nf" for mode 6, mode 7a, mode 7b, and mode 7c. on page 20, note 14, changed the sentence "1k means..." to "953 //22nf" means that there are a 953 resistor in parallel with a 22nf capacitor connecti ng the pin to sgnd; refer to figure 26. on page 23, current share; 2nd paragraph, changed the text "with a 1.0k resistor" to "with a 953 resistor and a 22nf capacitor". on page 24, "current share" 2nd paragraph, changed "1k " to "953 "; added a new paragraph "because of the typical 5.4v vcc and the internal 7.5k resistor between mode pin and vmon2 pin, the 953 resistor maintains vmon2 pin voltage close to 0.6v, thus output ovp/uvp (caused by vmon2 voltage too high or too low) will not be falsely triggered due to part to part variation at mass production. the 22nf capacitor is used to avoid output uvp/ovp triggered during input start-up." on page 25, "tracking function", 2nd paragraph, changed "vddq*(1+k)" to "vddq/(1+k)"; updated the 3rd paragraph "it is recommended to scale the target clkout voltage to 0. 612v (2% above 0.6v reference) with an external resistor divider from vddq. after start-up, the internal reference takes over to maintain the good regulation of vtt. the resistor divider ratio k of r7/r8 in figure 20 is based on the feedback divider of vddq (r1 and r2 values) and the 0.612v target clkout voltage as shown in equation 7:"; updated equation 7. may 23, 2014 fn8450.1 replaced figures 3 through 9 with figures showing efficiency up to a switching speed of 700khz. figure 1 on page 1: added sync pin and rsync resistor of 237k ? . electrical specifications table, ? synchronization frequency ? on page 8 , changed max from 500khz to 700khz. figure 23 on page 14: added rsync resistor of 140k ? . figure 24 on page 14: added rsync resistor of 174k ? . figure 25 on page 15: added rsync resistor of 100k ? . figure 26 on page 16: added rsync resistor of 237k ? . figure 28 on page 18: added rsync resistor of 237k ? . table 1 on page 19: updated the three columns of freq., rsyn c, load, to give more accurate information about optimum settings. figure 34 on page 24: updated the graph to include a wider switching frequency range. ? frequency synchronization and phase lock loop ? on page 24 : changed "the synchronized frequency can be from 350khz to 500khz" to "the synchronized frequency can be from 350khz to 700khz". march 12, 2014 fn8450.0 initial release
ISL8240M 30 fn8450.2 january 7, 2015 submit document feedback package outline drawing l26.17x17 26 lead quad flat no-lead pl astic package (punch qfn) rev 4, 10/12 bottom view side view top view s 17.80.2 17.00.2 17.80.2 17.00.2 a l l a r o u n d o f 1 0 ( m a x ) 0.25 7.50.2 r 0 . 2 5 2 3 4 5 6 7 1 8 9 10 12 13 14 11 151617181920 21 22 23 24 25 26 pin-to-pin distance (bottom view) 0.05 s ab 0.2 s ab s 0.2 s 0.03 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a:1.00.1 2 3 4 5 6 7 1 8 9 10 12 13 14 11 15 1617 1819 20 21 22 23 24 25 26 pin no. definition (top view) x4 a b 52x 0.50 (all of lead tips) 16x 1.750.05 (full lead) 16x 0.55 (full lead) 16x 0.70 (full lead) 3.50 3.50 3.50 2.37 2.77 5.33 4.93 3.66 8.95 0.38 0.80 4.00 3.35 3.35 14x 0.75 12x 1.07 2.97 0.10 0.25 4.93 8.95 0.10 0.25 5.33 0.10 0.10 0.10 0.10 3.50 0.70 0.38 12 10 1 12 10 1
ISL8240M 31 fn8450.2 january 7, 2015 submit document feedback * solder stencil pattern with s quare pads 1 of 2 (top view) solder stencil pattern with s quare pads 2 of 2 (top view) typical recommended land pattern (top view) 0 0 0 0 0.15 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 0.75 0.25 1.25 1.75 2.25 2.75 3.15 3.85 4.25 4.75 5.25 5.75 6.25 6.75 7.15 0.25 0.25 0.95 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 0.95 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 7.25 7.25 7.93 5.25 4.75 4.25 3.75 3.25 2.75 2.25 1.75 1.25 0.85 0.15 0.15 0.85 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 7.93 9.20 9.20 7.83 7.15 6.75 6.25 5.75 5.25 4.75 4.25 3.85 3.15 2.75 2.25 1.75 1.25 0.75 0.25 0.15 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 7.25 9.20 7.83 7.25 7.83 9.20 9.20 7.93 7.83 0 0 0.00 0 0.05 1.13 1.73 2.80 4.20 5.28 5.88 6.95 5.54 7.38 4.05 2.70 2.40 1.05 1.05 2.40 2.70 4.05 7.38 5.54 0.05 1.13 0.60 1.73 2.80 2.40 3.60 4.20 5.28 5.41 6.01 5.88 6.95 7.23 7.38 6.83 6.43 5.43 5.03 3.36 2.76 0.95 0.70 0.70 0.95 3.36 5.03 5.43 6.43 6.83 7.38 1.80 6.03 6.60 7.38 6.60 7.38 0.00 0 0 0.65 1.35 1.65 2.35 2.65 3.35 3.65 4.35 4.65 5.35 5.65 6.35 1.35 3.75 7.25 3.90 0.05 7.15 7.83 7.15 0.35 0.75 4.35 4.65 5.35 5.65 6.35 7.15 0.35 0.75 4.35 4.65 5.35 5.65 6.35 7.15 9.30 9.30 6.35 5.65 5.35 4.65 4.35 3.65 3.35 2.65 2.35 1.65 1.35 0.65 0.25 3.75 3.90 7.25 9.30 7.15 9.30 6.53 9.30 7.83 5.73 5.33 0.75 0.65 0.40 0.25 0.25 0.40 0.65 0.75 5.73 5.33 6.13 6.53 7.83 6.50 0.55 6.50 6.13 0.25 3.10 3.25 3.25 3.10 5.93 0.55 5.24 9.30 5.24 9.30 9.30 7.98 7.70 7.96 7.98 7.70 7.96 1 10 12 typical land pattern and stencil opening

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